Research Overview
The research addresses the joint design of wireless signal-processing algorithms and their hardware implementations, considering practical throughput, latency, energy consumption and hardware resources from the outset. The original research page uses 5G as its motivating example.
Requirements for 5G
The original 5G vision called for substantially higher throughput and lower latency than earlier mobile systems. The page uses a wider pipe as an analogy for higher data rates and a shorter pipe for reduced delay. Higher throughput can support buffering of video when channel conditions are favourable; lower latency can support responsive cloud-based processing for interactive applications.
These communication gains must be matched by base-station and handset signal processing, rather than being achieved solely in the radio transmission.
Candidates for 5G
The original page identifies six candidate technologies for 5G, each of which can increase the signal-processing workload.
- Millimetre-wave communication — more spectrum
- Small cells — more base stations
- Massive MIMO — more antennas
- Coordinated multipoint — more cooperation
- Cognitive radio — more intelligence
- New waveforms — greater spectral efficiency
Signal Processing Is the Bottleneck of 5G
Higher radio-link throughput alone is insufficient if signal processing cannot process the data at a comparable rate: the slowest stage constrains overall throughput. Similarly, transmission and processing delays add together, so fast transmission does not by itself guarantee low end-to-end latency.
The Conventional Approach
In the conventional approach, algorithm research and circuit implementation are often undertaken separately. Algorithms are first evaluated for transmission performance, bandwidth, throughput, latency, energy and computational complexity. Hardware designers subsequently consider resources, flexibility, processing throughput, latency and energy consumption.
Algorithmic complexity does not map directly to these hardware measures. Consequently, an algorithm described as low complexity may still be difficult to implement efficiently, producing mismatches between communication and processing capabilities.
The Southampton Wireless Approach
The Southampton Wireless approach jointly designs signal-processing algorithms and their hardware implementations. Hardware characteristics and implementation constraints are considered during algorithm design, enabling an architecture that can realise the algorithm’s potential in practice.
The objective is to align transmission and processing throughput, latency and energy consumption, rather than optimising algorithmic complexity in isolation.
Research Projects and Impact
AccelerComm
The group’s joint algorithm–hardware design approach was adopted by its spin-out company AccelerComm, established to commercialise research on the joint design of signal-processing algorithms and their hardware implementations.
Visit the AccelerComm website.
Research Projects
Related research and commercialisation projects include:
- Aid for Start-Ups — R. G. Maunder and T. Chen (Innovate UK) — Funding database
- Highly-parallel algorithms and architectures for high-throughput wireless receivers — R. G. Maunder and B. M. Al-Hashimi (EP/L010550/1) — Funding database
- Channel Decoder Architectures for Energy-Constrained Wireless Communication Systems: Holistic Approach — R. G. Maunder and B. M. Al-Hashimi (EP/J015520/1) — Funding database
Research Publications
The original page lists 18 publications on algorithm–hardware co-design, turbo and LDPC decoding, and energy-aware architectures. The links below lead to the Southampton research repository or publication record.
- M. F. Brejza, R. G. Maunder, B. M. Al-Hashimi and L. Hanzo. A Flexible Iterative Receiver Architecture for Wireless Sensor Networks: A Joint Source and Channel Coding Design Example
- R. Al-Dujaily, A. Li, R. G. Maunder, T. Mak, B. M. Al-Hashimi and L. Hanzo. A scalable turbo decoding algorithm for high-throughput network-on-chip implementation
- M. F. Brejza et al.. Exponential Golomb and Rice Error Correction codes for generalized near-capacity joint source and channel coding
- A. Li et al.. 1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications
- A. Li et al.. Implementation of a fully-parallel turbo decoder on a general-purpose graphics processing unit
- P. Hailes et al.. A survey of FPGA-based LDPC decoders
- X. Zuo et al.. Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: A tutorial and design example
- I. Perez-Andrade et al.. Stochastic computing improves the timing-error tolerance and latency of turbo decoders: Design guidelines and trade-offs
- A. Li et al.. VLSI implementation of fully-parallel LTE turbo decoders
- M. F. Brejza et al.. 20 years of turbo coding and energy-aware design guidelines for energy-constrained wireless applications
- R. G. Maunder. A fully-parallel turbo decoding algorithm
- M. F. Brejza et al.. Adaptive iterative detection for expediting the convergence of an iterative JSCC, and demodulator
- L. Li et al.. Energy-conscious turbo decoder design: A joint signal processing and transmit energy reduction approach
- I. Perez-Andrade et al.. Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders
- L. Li et al.. A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks
- L. Li et al.. Design of fixed-point processing based turbo codes using extrinsic information transfer charts
- L. Li et al.. An energy-efficient error correction scheme for IEEE 802.15.4 wireless sensor networks
- R. G. Maunder et al.. Iterative decoding for redistributing energy consumption in wireless sensor networks